1. Field of the Invention
The present invention relates to power management control, and more specifically, to an apparatus and method for power management control, wherein each power management state related to a Link that is in an active state between a chipset and a device, for example, an L0s and L1 state of Active State Power management (ASPM), which is a power management specification related to a Link between a chipset and a device, is disabled when a system enters a predetermined operating state, for example, an S3 or S4 state, and the disabled ASPM state (L0s or L1) is reactivated when the system is resumed, thereby supporting the L0s and L1 states which are Link power management states between the chipset and the device.
The Link between the chipset, i.e., a control unit, and the device is a Link of a PCI Express (PCI-E) scheme, and the power management ASPM states (L0s and L1) are power management states of the PCI-E.
2. Description of the Related Art
Hereinafter, a related art of the present invention will be described.
Recently, Links between chipsets such as north and south bridges and various devices of a computer system are established in a PCI Express (hereinafter, referred to as PCI-E) scheme. With the introduction of PCI-E, performance aspects such as data transmission speed between the chipsets and devices are greatly improved. However, there is a problem in that power consumed by the Links is also increased.
Accordingly, ASPM is proposed as a power management specifications of the Links between chipsets and devices. ASPM defines power management states of L0, L0s, L1, L2, and L3. When a system is in a normal operating state, i.e., when the system does not enter a standby mode, three states of L0, L0s, and L1 among the power management states may be supported.
Conventionally, ASPM states of a system are basically enabled or disabled by a BIOS regardless of an operating state of the system. Although the L0s and L1 states supported when a system is in a normal operating state (e.g., an S0 state of the ACPI power management specification) are functions basically supported by chipset manufacturers, states supported by chipset manufacturers may be different depending on completeness of a system and sometimes invite instability of the system.
Particularly, in a case where a Link power management state, i.e., L0s or L1 of ASPM, or both of them, between a control unit and a device of a system is enabled while the system is in a normal operating state, if the system operating state enters a standby mode (S3 or S4 of the ACPI power management specification), the Link power management state also enters L2 or L3. Then, the Link power management state may be any one of L0, L0s, and L1 states in the process of resuming the system operating state, which invites instability of the system, and thus a system hang (a phenomenon of halting the system) or Blue screen may occasionally occurs.
Accordingly, BIOSs are frequently designed not to support the ASPM functions or the L0s and L1 states between a chipset (north/south bridge), i.e., a control unit, and PCI Express devices (e.g., a video controller, Ethernet device, and wireless LAN).
Although the specification of I company is referred to for the terminologies and operation and power states described above, some terminologies are arbitrarily selected by the applicant in some specific cases. Since their operations and meanings are described in detail in corresponding descriptions of the invention, it is noted that the present invention should be understood through the operations and meanings of the terminologies, not merely by the terms of the terminologies.